2560 × 1600 @ 60 Hz
條件式可支援
頻寬可通過，但 pixel clock 位於 250–300 MHz 區間，MIPI DSC 3:1 必須由 host/driver 送出。
HARDWARE GATES
3 / 3 pass
Internal pixel clock
ANX7625 ceiling · 300 MHz
268.63 / 300 MHz
Pixel clock268.63 MHzCVT-RB estimate
Full timing2720 × 1646Htotal × Vtotal
DecisionPASSmust stay at or below 300 MHz
MIPI-DSI input
4 lanes · transport budget
2.15 / 6.00 Gbps
Transport demand2.15 Gbpscapacity 6.00 Gbps
DSC staterequired · 3:1 activeMIPI input compression
DecisionPASScompressed DSI rate is within lane capacity
eDP output link
uncompressed RGB888 · 8b/10b
8.39 / 13.50 Gbps
Wire demand8.39 Gbpspayload ÷ 0.80
Link capacity2 lanes × 5.40 = 10.80 Gbpsraw lane rate
DecisionPASSoutput link has enough raw capacity